This is about as rudimentary as it gets. Normally I would include a clock and reset but I m used to working with sequential design. Your module does not have clock or reset input and is strictly combinatorial.
You may need to debug my syntax :-) ... I don t know what your code is supposed to do since you didn t post anything from the body, but this should get you started. Good luck in your class.
start of vhdl below....
-- multiplier_testbench.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
entity multiplier_testbench is -- declare the testbench entity with no i/o
end multiplier;
architecture test_bench_arch of multiplier_testbench is
component multiplier -- if you have another module in the design you can instantiate additional components
port (
a : in std_logic_vector(3 downto 0); -- copy these from your entity declaration in the code
b : in std_logic_vector(3 downto 0);
cu : out std_logic_vector(7 downto 0);
cs : out std_logic_vector(7 downto 0)
);
end component;
-- at minimum you need to have signals that map to the i/o s of your module
signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal cu : std_logic_vector(7 downto 0);
signal cs : std_logic_vector(7 downto 0);
begin
-- now map the i/o s to the signals you declared
U1 : multiplier
port map (
a => a,
b => b,
cu => cu,
cs => output_cs
);
process : generate_stimulus
begin
a <= x"0";
b <= x"0";
wait for 20 ns;
-- multiply 5 x 2, hexadecimal notation
a <= x"5";
b <= x"2";
wait for 20 ns;
--multiply 6 x 3, binary notation
a <= "0110";
b <= "0011";
wait;
end process;
end test_bench_arch;