Question:
does anyone know what VHDL stands for?
Hmm...
2006-08-09 23:02:53 UTC
does anyone know what VHDL stands for?
Four answers:
Born_yesterday
2006-08-09 23:08:52 UTC
Very High Speed Integrated Circuit

Hardware

Description

Language
Krishna
2006-08-10 06:43:26 UTC
VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits.



VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.



The idea of being able to simulate these "documents" was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power efficiency, highest speed, or other requirements.



VHDL has a syntax that is essentially a subset of the Ada programming language, along with an added set of constructs to handle the parallelism inherent in hardware designs. VHDL is strongly-typed and case insensitive



VHDL is a fairly general-purpose programming language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements.



Good Luck!
2006-08-10 06:24:15 UTC
VHSIC Hardware Description Language
david
2006-08-10 06:08:35 UTC
Vaginal Hyper Disorder Location


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